The present invention relates to a method and apparatus for testing semiconductor devices which output a reference clock and data synchronized therewith.
Among a wide variety of semiconductor devices is a memory of the type that takes in data fed to a terminal together with an input clock and outputs a reference clock and data synchronized therewith. For example, a DDSRDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) takes in address data provided along with an input clock, then generates a reference clock synchronized with the input clock by a DLL (Delayed Locked Loop), and outputs data read out of specified addresses in synchronization with and together with the reference clock, thereby allowing ease in passing data to other devices through utilization of the timing of the reference clock.
FIG. 13 shows how this kind of memory device is read out. In FIG. 13A, reference characters DA, DB, DC, . . . denote pieces of output data from the memory device (data output via a certain pin). Reference characters TD1, TD2, . . . denote test cycles. In FIG. 13B reference character DQS denotes a reference clock that is output from the memory device. The pieces of data DA, DB, DC, . . . (a given one of which will hereinafter be typified by DQ) are output from the memory device in synchronization with the reference clock DQS. The reference clock DQS is used as a sync signal (a data strobe signal) for passing the data DA, DB, DC, . . . to other device when the memory device is in operation.
The testing of this kinds of memory device includes a test item measuring the time differences or intervals (phase differences) dI1, dI2, dI3, . . . between the leading or trailing edges (the leading edges in this example) of respective reference clocks DQS and the points of change of data. For example, the smaller the time differences, the faster the response and consequently the higher the level of performance characteristic. Hence, the above time differences are required to be smaller than a predetermined value Tdq. Further, the time intervals dJ1 and dJ2 between the leading edge of the reference clock DQS and the trailing edge of the data DQ are required to be longer than at least a predetermined value Tdr; this is a requirement for a memory device that is highly valued in the duration of data. The grade of the memory device under test depends on these time lengths.
While in operation, an external clock is applied to the memory device, which, in turn, generates the reference clock DQS based on the clock and outputs the data DQ in synchronization with the reference clock DQS. Accordingly, in the testing of the memory device by a tester, too, a clock is applied from the tester side to the memory device under test, which generates the reference clock DQS based on the clock and outputs the data DS as well as the reference clock DQS that is used for passing the data to other device. Since the point of change of the data DQ is defined with respect to the timing of the leading or training edge of the reference clock DQS, the test of the memory device measures and evaluates the time intervals dI1, dI2, dI3, . . . , or dJ1, dJ2, dJ3, . . . between the timing of the leading or trailing edge of the reference clocks DQS and the points of change of the pieces of data DA, DB, DC.
As described above, since the reference clock from the semiconductor device is generated therein, the timing of its generation is greatly affected by the device temperature; for instance, as depicted in FIG. 14, reference clocks DQS1, DQS2, DQS3, . . . from individual semiconductor devices under test A, B, C, . . . are phased apart. Moreover, in the case of memory devices, such a phase difference is caused not only by device-to-device temperature variation but also by the difference in the memory address accessed in the respective memory device and by what is called jitter J in the rise and fall timing of each reference clock that is caused by an increase in the device temperature due to an extended period of operation as indicated by the broken lines.
Accordingly, to measure the time intervals dI1, dI2, dI3, . . . , or dJ1, dJ2, dJ3, . . . between the timing of the leading or trailing edge of the reference clock DQS and the points of change of the data DA, DB, DC, . . . , it is necessary to provide as a known value the timing of the leading or trailing edge of the reference clock DQS which is output from each semiconductor device.
The timing of generation of the reference clock DQS could be obtained as a known value by: applying all test patterns (over all test cycles) to each DUT in a sequential order; measuring the timing of generation of the reference clock DQS that is generated at the time of reading out of each test pattern; storing the measured values in a memory or the like; and conducting the actual test after obtaining data on the timing of generation of the reference clock DQS over all the test cycles. That is, the timing of generation of the reference clock DQS and the point of change of the output data are measured with reference to the operating clock that defines the test cycle of the tester.
In the actual test, the timing of generation of the reference clock DQS prestored in the memory is read out thereof for each test cycle, and the time difference (the phase difference relative to the test cycle) from the read-out timing of generation of the reference clock DSQ to the timing of the leading or trailing edge of each data is measured. In the testing of the timing of the leading edge of the data DQ, the timing is judged as “pass” or “fail” depending on whether the phase difference is smaller than the predetermined value Tdq or not. In the testing of the trailing edge of the data DQ, it is necessary only to decide whether the phase difference between the timing of generation of the reference clock DQS and the timing of the trailing edge of the data DQ is larger than the predetermined value Tdr.
In the case of conducting the actual test after obtaining the timing of generation of the reference clock DQS for all test cycles as described above, the time for the test is essentially twice longer than usual.
Further, since the timing of generation of the reference clock DQS contains random jitter J as depicted in FIG. 14, pre-measuring the generation timing over all the test cycles does not guarantee repeatability and hence reliability of the measured values. Accordingly, the test using such measured values is inevitably low in accuracy and consequently in reliability.